Invention Grant
- Patent Title: Powermap optimized thermally aware 3D chip package
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Application No.: US15048140Application Date: 2016-02-19
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Publication No.: US10032695B2Publication Date: 2018-07-24
- Inventor: Madhu Krishnan Iyengar , Teck-Gyu Kang , Christopher Gregory Malone , Norman Paul Jouppi
- Applicant: Google Inc.
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Honigman Miller Schwartz and Cohn LLP
- Main IPC: H01L23/473
- IPC: H01L23/473 ; H01L23/04 ; H01L23/367 ; H01L23/373 ; H01L23/498 ; H01L25/18 ; H01L23/44 ; H01L25/065

Abstract:
A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.
Public/Granted literature
- US20170243806A1 Powermap Optimized Thermally Aware 3D Chip Package Public/Granted day:2017-08-24
Information query
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