Invention Grant
- Patent Title: Memory protection at a thread level for a memory protection key architecture
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Application No.: US15088836Application Date: 2016-04-01
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Publication No.: US10037288B2Publication Date: 2018-07-31
- Inventor: Francesc Bernat Guim , David A. Koufaty , Andrea Pellegrini , Rajesh M. Sankaran
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/14 ; G06F12/1009 ; G06F21/62 ; G06F13/00 ; G06F13/28

Abstract:
A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.
Public/Granted literature
- US20170286326A1 MEMORY PROTECTION AT A THREAD LEVEL FOR A MEMORY PROTECTION KEY ARCHITECTURE Public/Granted day:2017-10-05
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