公开(公告)号：US20170286326A1

公开(公告)日：2017-10-05

申请号：US15088836

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Francesc Bernat Guim ,  David A. Koufaty ,  Andrea Pellegrini ,  Rajesh M. Sankaran

IPC: G06F12/14 ,  G06F21/62 ,  G06F12/10

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F12/1081 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.

公开(公告)号：US10564972B1

公开(公告)日：2020-02-18

申请号：US16147066

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Vadim Sukhomlinov ,  Francesc Bernat Guim

IPC: G06F9/30 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897

Abstract: An apparatus and method for efficiently reclaiming demoted cache lines. For example, one embodiment of a processor comprises: a cache hierarchy including at least one Level 1 (L1) cache and one or more lower level caches; a decoder to decode a cache line (CL) demote instruction specifying at least a first cache line; and execution circuitry to demote the first cache line responsive to the CL demote instruction, the execution circuitry to implement a writeback operation on the first cache line if the first cache line has been modified and homed in a specified memory tier or a default memory tier specified in a register.

公开(公告)号：US10037288B2

公开(公告)日：2018-07-31

申请号：US15088836

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Francesc Bernat Guim ,  David A. Koufaty ,  Andrea Pellegrini ,  Rajesh M. Sankaran

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1009 ,  G06F21/62 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F12/1081 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.