A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.