公开(公告)号：US10037819B2

公开(公告)日：2018-07-31

申请号：US15484244

申请日：2017-04-11

Applicant: SK hynix Inc.

Inventor： Jae II Kim

IPC: G11C11/402 ,  G11C29/00 ,  G11C11/406 ,  G11C8/08 ,  G11C29/52

CPC classification number: G11C29/783 ,  G11C8/08 ,  G11C11/402 ,  G11C11/40611 ,  G11C29/52

Abstract: A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.

公开(公告)号：US09183899B2

公开(公告)日：2015-11-10

申请号：US14148254

申请日：2014-01-06

Applicant: SK hynix Inc.

Inventor： Jae II Kim

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/106 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/222

Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.

Abstract translation: 半导体集成电路可以包括：分隔成第一区域和第二区域的存储器块; 数据锁存单元，被配置为响应于控制信号锁存从所述存储块输出的数据; 以及控制电路，被配置为响应于连续输入的访问所述第一区域或所述第二区域的列访问信号而生成分成奇数阶和偶数阶的源信号，并且响应于所述源信号产生所述控制信号 。