- Patent Title: Memory circuit with a bistable circuit and a non-volatile element
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Application No.: US15501247Application Date: 2015-08-06
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Publication No.: US10049740B2Publication Date: 2018-08-14
- Inventor: Satoshi Sugahara , Yusuke Shuto , Shuichiro Yamamoto
- Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY , KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY
- Applicant Address: JP Saitama JP Kanagawa
- Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY,KANAGAWA INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY,KANAGAWA INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee Address: JP Saitama JP Kanagawa
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2014-164526 20140812
- International Application: PCT/JP2015/072392 WO 20150806
- International Announcement: WO2016/024527 WO 20160218
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C14/00 ; G11C11/419 ; G11C11/16

Abstract:
A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.
Public/Granted literature
- US20170229179A1 MEMORY CIRCUIT Public/Granted day:2017-08-10
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