A double buffer (four pages×2 system) constituted by a DSP program buffer (D-RAM) and a prefetch program buffer (D-RAM) is provided, and burst access is performed collectively for four samplings from the prefetch program buffer (D-RAM). When this burst access is performed, a decline in performance caused by latency that occurs each time an external memory (DDR-SDRAM) is accessed is avoided by accessing with sequential addresses.