Invention Grant
- Patent Title: Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)
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Application No.: US15122630Application Date: 2014-06-16
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Publication No.: US10068874B2Publication Date: 2018-09-04
- Inventor: Donald W. Nelson , M Clair Webb , Patrick Morrow , Kimin Jun
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2014/042574 WO 20140616
- International Announcement: WO2015/195082 WO 20151223
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L25/065 ; H01L23/538 ; H01L23/00 ; H01L25/00

Abstract:
A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.
Public/Granted literature
- US20170069598A1 METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT USE OF THRU SILICON VIAS (TSV) Public/Granted day:2017-03-09
Information query
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