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    Vertical diode in stacked transistor architecture
    1.
    发明授权
    Vertical diode in stacked transistor architecture 有权

    公开(公告)号：US11616056B2

    公开(公告)日：2023-03-28

    申请号：US16649712

    申请日：2018-01-18

    申请人： INTEL CORPORATION

    发明人： Aaron D. Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

    IPC分类号： H01L27/06 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861

    摘要： An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

    Three dimensional integrated circuits with stacked transistors
    2.
    发明授权
    Three dimensional integrated circuits with stacked transistors 有权

    公开(公告)号：US11605565B2

    公开(公告)日：2023-03-14

    申请号：US16236156

    申请日：2018-12-28

    申请人： Intel Corporation

    发明人： Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Aaron Lilak ,  Kimin Jun ,  Brennen Mueller ,  Ehren Mannebach ,  Anh Phan ,  Patrick Morrow ,  Hui Jae Yoo ,  Jack T. Kavalieros

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/423

    摘要： Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

    GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA SELECTIVE DIELECTRIC DEPOSITION STRUCTURE
    3.
    发明申请
    GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA SELECTIVE DIELECTRIC DEPOSITION STRUCTURE 有权

    公开(公告)号：US20230073078A1

    公开(公告)日：2023-03-09

    申请号：US17445856

    申请日：2021-08-25

    申请人： Intel Corporation

    发明人： Willy Rachmady ,  Sudipto Naskar ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Marko Radosavljevic ,  Nicole K. Thomas ,  Patrick Morrow ,  Urusa Alaan

    IPC分类号： H01L27/12

    摘要： An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

    Stacked trigate transistors with dielectric isolation between first and second semiconductor fins
    4.
    发明授权
    Stacked trigate transistors with dielectric isolation between first and second semiconductor fins 有权

    公开(公告)号：US11594533B2

    公开(公告)日：2023-02-28

    申请号：US16455667

    申请日：2019-06-27

    申请人： Intel Corporation

    发明人： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Ehren Mannebach ,  Jack T. Kavalieros

    IPC分类号： H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

    摘要： A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

    Microelectronic assemblies
    5.
    发明授权
    Microelectronic assemblies 有权

    公开(公告)号：US11348897B2

    公开(公告)日：2022-05-31

    申请号：US16647863

    申请日：2017-12-29

    申请人： Intel Corporation

    发明人： Adel A. Elsherbini ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan ,  Patrick Morrow ,  Kimin Jun ,  Brennen Mueller ,  Paul B. Fischer

    IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L25/00

    摘要： Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

    MULTI-LEVEL SPIN LOGIC
    8.
    发明申请
    MULTI-LEVEL SPIN LOGIC 有权

    公开(公告)号：US20210143819A1

    公开(公告)日：2021-05-13

    申请号：US17152552

    申请日：2021-01-19

    申请人： Intel Corporation

    发明人： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

    IPC分类号： H03K19/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H03K19/18

    摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

    Multi-level spin logic
    9.
    发明授权
    Multi-level spin logic 有权

    公开(公告)号：US10944399B2

    公开(公告)日：2021-03-09

    申请号：US15779074

    申请日：2016-12-23

    申请人： Intel Corporation

    发明人： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

    IPC分类号： H03K19/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H03K19/18

    摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.