Invention Grant
- Patent Title: Method of manufacturing MOS transistor with stack of cascaded nanowires
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Application No.: US14387830Application Date: 2013-08-06
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Publication No.: US10068990B2Publication Date: 2018-09-04
- Inventor: Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
- Applicant: Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
- Applicant Address: CN Beijing
- Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
- Current Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
- Current Assignee Address: CN Beijing
- Agency: Christensen, Fonder, Dardi & Herbert PLLC
- Priority: CN201310274977 20130702
- International Application: PCT/CN2013/080893 WO 20130806
- International Announcement: WO2015/000205 WO 20150108
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/66 ; H01L29/786 ; H01L29/423

Abstract:
A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.
Public/Granted literature
- US20160233317A1 METHOD OF MANUFACTURING MOS TRANSISTOR WITH STACK OF CASCADED NANOWIRES Public/Granted day:2016-08-11
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