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1.
公开(公告)号:US20240345488A1
公开(公告)日:2024-10-17
申请号:US18294989
申请日:2021-12-29
发明人: Dandan Han , Yayi Wei
IPC分类号: G03F7/00
CPC分类号: G03F7/70516 , G03F7/70141 , G03F7/70258 , G03F7/70558
摘要: A method for fast precise optical calibration on a photolithography system, including: determining a fitting relationship for a spot width corresponding to a point light source based on distribution of field strength generated by the point light source at an exit plane of a focusing element; determining, based on the fitting relationship, a first correspondence between the spot width and a parameter for exposing a photoresist, where the spot width in the first correspondence is for optical microscopy; determining a first spot-width dataset for the point light source based on an optical microscopic image of a spot-mapping pattern on a surface of the photoresist; determining, based on the first spot-width dataset, a second correspondence between the spot width and the parameter; and determining the first correspondence as a means for determining the parameter, when the first correspondence and the second correspondence meet a preset condition.
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公开(公告)号:US20240334838A1
公开(公告)日:2024-10-03
申请号:US18293846
申请日:2022-03-02
发明人: Guozhong Xing , Long Liu , Xuefeng Zhao , Di Wang , Huai Lin , Hao Zhang , Ziwei Wang
CPC分类号: H10N50/10 , G11C5/063 , G11C11/161 , G11C11/1673 , G11C11/1675 , H10B61/20 , H10N50/20 , H10N50/85 , H10N52/101
摘要: The present disclosure provides an SOT-MRAM memory cell, including: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain of which is connected to the orbital Hall effect layer; and a second transistor, a drain of which is connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.
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公开(公告)号:US20240305297A1
公开(公告)日:2024-09-12
申请号:US18258706
申请日:2020-12-25
发明人: Zhi LI , Jianzhong ZHAO , Yumei ZHOU
IPC分类号: H03K19/0175
CPC分类号: H03K19/0175
摘要: Provided is a signal driving system with a constant slew. The signal driving system with the constant slew includes: a step voltage generation unit configured to provide multiplex arithmetic gradient voltage signals; a multiplexer, wherein an input end of the multiplexer is connected to the step voltage generation unit to receive the multiplex arithmetic gradient voltage signals, and another input end of the multiplexer is connected to a control signal generation unit, and the multiplexer is configured to selectively output the multiplex arithmetic gradient voltage signals under a control of a control signal generated by the control signal generation unit; a voltage following unit connected to the multiplexer, wherein the voltage following unit is configured to serve as an isolation and improve a driving ability; and an output following unit connected to the voltage following unit, wherein the output following unit is configured to drive a subsequently-connected load unit.
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公开(公告)号:US20240260488A1
公开(公告)日:2024-08-01
申请号:US18559755
申请日:2022-03-15
发明人: Xiaoxin XU , Wenxuan SUN , Jie YU , Jinru LAI , Xu ZHENG , Danian DONG
CPC分类号: H10N70/041 , H10N70/023 , H10N70/026 , H10N70/25 , H10N70/8836
摘要: A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.
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公开(公告)号:US12027457B2
公开(公告)日:2024-07-02
申请号:US17836934
申请日:2022-06-09
发明人: Huilong Zhu
IPC分类号: H01L23/522 , H01L21/768 , H01L23/532
CPC分类号: H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/53204
摘要: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.
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公开(公告)号:US20240191168A1
公开(公告)日:2024-06-13
申请号:US18529820
申请日:2023-12-05
发明人: Junjie Li , Na Zhou , Enxu Liu , Jianfeng Gao , Junfeng Li , Jun Luo , Wenwu Wang
CPC分类号: C12M25/04 , G03F7/70383
摘要: A method for manufacturing a nanostructure and a nanostructure are disclosed. The method for manufacturing the nanostructure includes first alternately and periodically stacking a first material layer and a second material layer on a substrate to form a stacked layer, then forming a slot pattern on an upper surface of the stacked layer and etching the stacked layer to an upper surface of the substrate to transfer the slot pattern to the stacked layer, filling the slot pattern in the stacked layer with a molding material, and removing the first material layer or the second material layer left in the stacked layer, so as to form nanopores arranged in an array in the stacked layer.
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公开(公告)号:US20240184217A1
公开(公告)日:2024-06-06
申请号:US17784064
申请日:2021-12-29
发明人: Jian Xu , Yayi Wei , Shang Yang
IPC分类号: G03F7/00
CPC分类号: G03F7/70558 , G03F7/70391 , G03F7/70516
摘要: A method and an apparatus for correcting a proximity effect of an electron beam. An initial dose of the electron beam is preset for each exposed square, and proximity effect energy representing an influence of exposing all exposed squares other than a current exposed square on the current exposed is calculated. A corrected dose of the electron beam for the current exposed square is then calculated, and the corrected dose for each exposed square in the electron beam exposure layout matrix is successively calculated. Then, the above calculation iterates for T times to obtain a final corrected dose of the electron beam for each exposed square.
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公开(公告)号:US20240164110A1
公开(公告)日:2024-05-16
申请号:US17783627
申请日:2021-12-23
申请人: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人: Weixing HUANG , Huilong ZHU
IPC分类号: H10B51/30
CPC分类号: H10B51/30
摘要: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. In embodiments of the present disclosure, the C-shaped ferroelectric layer serves as a memory layer of the memory device. A C-shaped channel is capable to increase an electric field within the ferroelectric layer under a fixed gate voltage, so as to increase a memory window of the semiconductor device. Moreover, the C-shaped channel is capable to reduce a gate voltage decreased under a fixed storage window of the whole semiconductor device, so as to reduce power consumption of the semiconductor device. Hence, a performance of the memory device is improved.
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9.
公开(公告)号:US20240120382A1
公开(公告)日:2024-04-11
申请号:US18262193
申请日:2021-11-26
申请人: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人: Huilong Zhu , Qi Wang
IPC分类号: H01L29/08 , H01L29/04 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H10B12/00
CPC分类号: H01L29/0847 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78642 , H01L29/78696 , H10B12/0335 , H10B12/05 , H10B12/315 , H10B12/482 , H10B12/488
摘要: A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.
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10.
公开(公告)号:US20240087628A1
公开(公告)日:2024-03-14
申请号:US18259747
申请日:2020-12-30
发明人: Guozhong XING , Huai LIN , Feng ZHANG , Di WANG , Long LIU , Changqing XIE , Ling LI , Ming LIU
CPC分类号: G11C11/161 , G11C11/1673 , G11C11/1675 , H03K19/21 , H10B61/00 , H10N50/20 , H10N50/80 , H10N50/85
摘要: A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.
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