公开(公告)号：US09281398B2

公开(公告)日：2016-03-08

申请号：US14355664

申请日：2012-07-03

Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US09115308B2

公开(公告)日：2015-08-25

申请号：US13698029

申请日：2012-08-03

Applicant: Xinhui Zhong ,  Hongji Huang ,  Kuancheng Lee ,  Xiaolong Ma

Inventor： Xinhui Zhong ,  Hongji Huang ,  Kuancheng Lee ,  Xiaolong Ma

IPC: C09K19/54 ,  C09K19/30 ,  C09K19/12 ,  C09K19/06 ,  C09K19/32 ,  C09K19/04

CPC classification number: C09K19/54 ,  C09K19/062 ,  C09K19/322 ,  C09K2019/0448 ,  C09K2019/122 ,  C09K2019/3009

Abstract: A liquid crystal medium composition of liquid crystal display includes: a negative liquid crystal material, reactive monomer, an initiator, and a stabilizer. The initiator functions to induce photo polymerization of the reactive monomer. The initiator has a molecular structure comprising aromatic rings, carbonyl groups connected to the aromatic rings, and substituted moieties connected to the aromatic rings. The initiator lowers the activation energy of chain initiation reaction of the polymerization of reactive monomer to allow the photo polymerization of the reactive monomer to take place in a wider wavelength range of 200-450 nm, so as to reduce the required intensity and luminance of ultraviolet light and to speed up the reaction of the reactive monomers and also to provide a uniform result of reaction, to reduce the destruction that the ultraviolet light causes on the material of alignment layer and the liquid crystal material, and to improve stability of the panel.

Abstract translation: 液晶显示器的液晶介质组合物包括负极性液晶材料，反应性单体，引发剂和稳定剂。 引发剂用于引发反应性单体的光聚合。 引发剂具有包含芳族环，与芳环连接的羰基和与芳环连接的取代部分的分子结构。 引发剂降低反应性单体聚合引发反应的活化能，使反应性单体的光聚合在较宽的波长范围内发生，从而降低紫外线的强度和亮度 并且加速反应性单体的反应，并且还提供均匀的反应结果，以减少紫外光对取向层和液晶材料的材料的破坏，并提高面板的稳定性。

公开(公告)号：US08796744B1

公开(公告)日：2014-08-05

申请号：US13812504

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/775

CPC classification number: H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。

公开(公告)号：US20130335659A1

公开(公告)日：2013-12-19

申请号：US13638078

申请日：2012-06-28

Applicant: Xiaolong Ma ,  Hong-Ji Huang

Inventor： Xiaolong Ma ,  Hong-Ji Huang

IPC: G02F1/1343

CPC classification number: G02F1/134363 ,  G02F1/1333 ,  G02F1/133711 ,  G02F2001/133726 ,  G02F2001/133765

Abstract: The present invention provides to an in-plane-switching (IPS) mode liquid crystal panel, which comprises: a first substrate, a second substrate, a coplanar transparent electrode layer and a liquid crystal layer. The first and second substrates have a first alignment film and a second alignment film, respectively. The coplanar transparent electrode layer is disposed onto the second alignment film. The liquid crystal layer is disposed in a space between the first alignment film of the first substrate and the coplanar transparent electrode layer of the second substrate. The liquid crystal layer comprises dual-frequency liquid crystal molecules and dual-frequency reactive mesogens/monomers. The liquid crystal panel of the present invention can overcome the problems of pollution and static electricity generated from the rubbing alignment in the in-plane-switching (IPS) mode, so as to simplify the manufacturing process and provide the advantages of high contrast, high response speed and wide viewing angle.

Abstract translation: 本发明提供一种面内切换（IPS）模式液晶面板，其包括：第一基板，第二基板，共面透明电极层和液晶层。 第一基板和第二基板分别具有第一取向膜和第二取向膜。 共面透明电极层设置在第二取向膜上。 液晶层设置在第一基板的第一取向膜和第二基板的共面透明电极层之间的空间中。 液晶层包括双频液晶分子和双频反应性介晶/单体。 本发明的液晶面板可以克服在平面切换（IPS）模式中由摩擦取向产生的污染和静电的问题，从而简化制造过程，并提供高对比度，高 响应速度和广视角。

公开(公告)号：US08570471B2

公开(公告)日：2013-10-29

申请号：US13318352

申请日：2011-05-19

Applicant: Kuan-Cheng Lee ,  Xiaolong Ma

Inventor： Kuan-Cheng Lee ,  Xiaolong Ma

IPC: G02F1/1337

CPC classification number: G02F1/133351 ,  G02F1/133788 ,  G02F1/1395

Abstract: The present invention discloses a manufacturing method of an Optically Compensated Bend (OCB) liquid crystal panel, which comprises: an arranging step S1 for alternately arranging a plurality of thin-film transistor (TFT) substrates and a plurality of color filter (CF) substrates, the TFT substrates and the CF substrates are coated with optical alignment material; a light irradiating step S2 for using an ultraviolet (UV) light source to irradiate the TFT substrates and the CF substrates so that alignment films of predetermined alignment directions are formed by the optical alignment material on the TFT substrates and the CF substrates; and an attaching step S3 for attaching each of the TFT substrates and an adjacent one of the CF substrates in such a way that an alignment direction of the TFT substrate is the same as that of the corresponding CF substrate and filling an OCB liquid crystal layer therebetween to form a plurality of OCB liquid crystal panels. For the OCB liquid crystal panel of the present invention, the TFT substrates and the CF substrates are optically aligned in a contactless way, the efficiency of each irradiation is high, which is favorable for mass production.

Abstract translation: 本发明公开了一种光学补偿弯曲（OCB）液晶面板的制造方法，其包括：用于交替布置多个薄膜晶体管（TFT）基板和多个滤色器（CF）基板）的布置步骤S1 ，TFT基板和CF基板涂覆有光学取向材料; 用于使用紫外线（UV）光源照射TFT基板和CF基板的光照射步骤S2，使得通过TFT基板和CF基板上的光学取向材料形成预定取向方向的取向膜; 以及附接步骤S3，用于将TFT基板和相邻的一个CF基板以使得TFT基板的取向方向与相应的CF基板相同并且在其间填充OCB液晶层的方式 以形成多个OCB液晶面板。 对于本发明的OCB液晶面板，TFT基板和CF基板以非接触方式进行光学对准，每次照射的效率高，这有利于批量生产。

公开(公告)号：US20130208221A1

公开(公告)日：2013-08-15

申请号：US13519652

申请日：2012-05-22

Applicant: Xiaolong Ma

Inventor： Xiaolong Ma

IPC: G02F1/1337 ,  H01J9/26 ,  G02F1/1339

CPC classification number: G02F1/1337 ,  G02F1/1339

Abstract: The invention provides an LCD panel, an LCD device, and a method for manufacturing a panel. The LCD panel includes an upper substrate and a lower substrate which are arranged opposite to each other. Opposite inner sides of the upper substrate and the lower substrate are respectively provided with a layer of alignment film, a sealant is arranged between the upper substrate and the lower substrate, the alignment film is arranged to extend outside the sealant area, and a surface of the alignment film exposed outside the sealant is provided with a sealing layer. In the invention, the alignment film is arranged to extend outside the sealant, which enable a narrow frame to be used to the LCD panel, and improves the utilization rate of the substrate; moreover, the alignment film exposed outside the sealant is sealed, to completely isolate the alignment film from the outside air; thus, the alignment film cannot be hydrolyzed because of absorbing the outside vapor, thereby ensuring the display quality.

Abstract translation: 本发明提供一种LCD面板，LCD装置以及面板制造方法。 LCD面板包括彼此相对布置的上基板和下基板。 上基板和下基板的相对的内侧分别设置有一层取向膜，在上基板和下基板之间设置密封剂，配向膜布置成延伸到密封剂区域的外侧， 暴露在密封剂外部的取向膜设置有密封层。 在本发明中，取向膜布置成在密封剂的外部延伸，这使得可以将窄框架用于LCD面板，并提高基板的利用率; 此外，暴露在密封剂外部的取向膜被密封，以使取向膜与外部空气完全隔离; 因此，由于吸收外部蒸气，取向膜不能水解，从而确保了显示质量。

公开(公告)号：US20130092946A1

公开(公告)日：2013-04-18

申请号：US13380047

申请日：2011-11-09

Applicant: Xiaolong Ma ,  Hungjui Chen ,  Tsunglung Chang

Inventor： Xiaolong Ma ,  Hungjui Chen ,  Tsunglung Chang

IPC: H01L27/15 ,  H01L21/02

CPC classification number: G02F1/136259 ,  G02F1/136204 ,  G02F1/136286 ,  G02F2001/136263 ,  G02F2001/136272 ,  G02F2201/18 ,  G02F2201/40 ,  G02F2201/506 ,  H01L27/02 ,  H01L27/124

Abstract: The present invention provides a TFT-LCD array substrate having a gate-line metal layer, a data-line metal layer crossing the gate-line metal layer and a plurality of layers covering a periphery of the gate-line metal layer and the data-line metal layer; the gate-line metal layer has first gate lines and second gate lines parallel and alternately arranged, the date-line metal layer has first data lines and second data lines parallel and alternately arranged; the first gate line and the second gate line are electrically connected; the first data line and the second data line are electrically connected. The present invention further provides a manufacturing method of the TFT-LCD array substrate. Implementing the TFT-LCD array substrate and the manufacturing method can reduce the occurrence of line-broken in the active array of TFT-LCD, increase the aperture ratio of the product and enhance yield rate of the products.

Abstract translation: 本发明提供一种TFT-LCD阵列基板，其具有栅线金属层，与栅线金属层交叉的数据线金属层和覆盖栅极线金属层周边的多个层， 线金属层; 栅线金属层具有平行且交替布置的第一栅极线和第二栅极线，日期线金属层具有平行并交替布置的第一数据线和第二数据线; 第一栅极线和第二栅极线电连接; 第一数据线和第二数据线电连接。 本发明还提供了TFT-LCD阵列基板的制造方法。 实施TFT-LCD阵列基板及其制造方法可以减少TFT-LCD有源阵列中线路断裂的发生，提高产品的开口率，提高产品的产量。

公开(公告)号：US20160233317A1

公开(公告)日：2016-08-11

申请号：US14387830

申请日：2013-08-06

Applicant: Huaxiang YIN ,  Xiaolong MA ,  Weijia XU ,  Qiuxia XU ,  Huilong ZHU

Inventor： Huaxiang YIN ,  Xiaolong MA ,  Weijia XU ,  Qiuxia XU ,  Huilong ZHU

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/66439 ,  H01L29/78696

Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. he cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Abstract translation: 具有堆叠的纳米线的MOS晶体管及其制造方法。 晶体管可以包括在衬底上沿第一方向延伸的级联纳米线的叠层; 沿着第二方向跨越纳米线堆叠延伸的栅极堆叠; 源极和漏极区域，设置在栅极堆叠的第二方向的相对侧上; 以及由源区和漏区之间的纳米线叠层构成的沟道区。 他级联的纳米线可以通过反复的蚀刻操作形成，横向蚀刻然后填充槽，从而增加通道的有效宽度，增加有效导电部分的总面积，从而提高驱动电流。

公开(公告)号：US08889519B2

公开(公告)日：2014-11-18

申请号：US13812499

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/165 ,  H01L21/268 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02675 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源区和漏区中的至少一个包括GeSn合金。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为 有效提高了设备​​驱动能力。

公开(公告)号：US20140197376A1

公开(公告)日：2014-07-17

申请号：US13812504

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L29/775

CPC classification number: H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。