Invention Grant
- Patent Title: Method, apparatus and system for voltage compensation in a semiconductor wafer
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Application No.: US15013956Application Date: 2016-02-02
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Publication No.: US10069490B2Publication Date: 2018-09-04
- Inventor: Sukeshwar Kannan , Luke England , Mehdi Sadi
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H03K3/017
- IPC: H03K3/017 ; H03K5/003 ; H03K5/156 ; G05F1/10 ; G06F1/26 ; H02M3/158 ; H02M3/156

Abstract:
At least one method, apparatus and system disclosed involves performing a dynamic voltage compensation in an integrated circuit. A first voltage on a first portion of an integrated circuit is received. A second voltage on a second portion of the integrated circuit is monitored. A determination is made as to whether the second voltage fell below the first voltage by a predetermined margin. A feedback adjustment of the of the second voltage is performed in response to a determination that the second voltage fell below the first voltage by the predetermined margin; the feedback adjustment comprises performing a step up of the second voltage.
Public/Granted literature
- US20170222634A1 METHOD, APPARATUS AND SYSTEM FOR VOLTAGE COMPENSATION IN A SEMICONDUCTOR WAFER Public/Granted day:2017-08-03
Information query
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