Invention Grant
- Patent Title: Integrated JFET structure with implanted backgate
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Application No.: US15195287Application Date: 2016-06-28
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Publication No.: US10079294B2Publication Date: 2018-09-18
- Inventor: Alexei Sadovnikov , Doug Weiser , Mattias Erik Dahlstrom , Joel Martin Halbert
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/265 ; H01L21/324 ; H01L23/535 ; H01L29/808

Abstract:
A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.
Public/Granted literature
- US20170373171A1 INTEGRATED JFET STRUCTURE WITH IMPLANTED BACKGATE Public/Granted day:2017-12-28
Information query
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