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    ASYMMETRICAL CHANNEL FLOATING GATE THREE-STATE ONE-TIME PROGRAMMABLE NONVOLATILE MEMORY
    3.
    发明申请
    ASYMMETRICAL CHANNEL FLOATING GATE THREE-STATE ONE-TIME PROGRAMMABLE NONVOLATILE MEMORY 有权

    公开(公告)号：US20250081449A1

    公开(公告)日：2025-03-06

    申请号：US18240580

    申请日：2023-08-31

    Applicant: Texas Instruments Incorporated

    Inventor： Jack Qian ,  Doug Weiser ,  Tamer San

    IPC: H10B20/25 ,  G11C17/16 ,  G11C17/18

    Abstract: An electronic device with a non-volatile memory includes a non-volatile memory (NVM) cell selectively programmable to change a program state from a first state to a second state or to a third state, and may also include a write circuit configured to selectively program the NVM cell to change the program state from the first state to the second state by applying a programming voltage signal to a first source/drain region and to change the program state from the first state to the third state by applying the programming voltage signal to a second source/drain region. A read circuit is configured to identify the program state of the NVM memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.

    BURIED CHANNEL SEMICONDUCTOR DEVICE INCLUDING ENERGY BARRIER MODULATION REGION(S)
    4.
    发明申请
    BURIED CHANNEL SEMICONDUCTOR DEVICE INCLUDING ENERGY BARRIER MODULATION REGION(S) 有权

    公开(公告)号：US20240405125A1

    公开(公告)日：2024-12-05

    申请号：US18326628

    申请日：2023-05-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jack G. Qian ,  Doug Weiser ,  Kemal T. San

    IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66

    Abstract: The present disclosure generally relates to a buried channel semiconductor device that includes one or more energy barrier modulation regions. In an example, a device includes a source/drain region, an energy barrier modulation region, a channel covering surface region, and a gate structure. The source/drain region is in a doped region in a semiconductor substrate that has an upper surface. The energy barrier modulation and channel covering surface regions are in the doped region and at the upper surface. The gate structure is over the upper surface. The energy barrier modulation and channel covering surface regions underlie the gate structure. The energy barrier modulation region is laterally between the source/drain and channel covering surface regions. The doped and energy barrier modulation regions are doped with a first conductivity type, and the source/drain and channel covering surface regions are doped with a second conductivity type opposite from the first conductivity type.

    Integrated JFET structure with implanted backgate
    5.
    发明授权
    Integrated JFET structure with implanted backgate 有权

    公开(公告)号：US10522663B2

    公开(公告)日：2019-12-31

    申请号：US15999542

    申请日：2018-08-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

    IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/06

    Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

    Programmable non-volatile memory with low off current
    9.
    发明授权
    Programmable non-volatile memory with low off current 有权

    公开(公告)号：US10374100B2

    公开(公告)日：2019-08-06

    申请号：US15637986

    申请日：2017-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Doug Weiser ,  Jack G. Qian

    IPC: H01L29/788 ,  H01L29/02 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11517 ,  H01L21/8234 ,  H01L21/265

    Abstract: In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.

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