Invention Grant
- Patent Title: Memory cell imprint avoidance
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Application No.: US15645106Application Date: 2017-07-10
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Publication No.: US10083732B2Publication Date: 2018-09-25
- Inventor: Alessandro Calderoni , Durai Vishak Nirmal Ramaswamy , Kirk Prall , Ferdinando Bedeschi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C11/22
- IPC: G11C11/22 ; G11C29/52 ; G06F11/10

Abstract:
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.
Public/Granted literature
- US20170365323A1 MEMORY CELL IMPRINT AVOIDANCE Public/Granted day:2017-12-21
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