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公开(公告)号：US20240265963A1
公开(公告)日：2024-08-08
申请号：US18637057
申请日：2024-04-16
发明人： Ferdinando Bedeschi
IPC分类号： G11C11/4096 , G11C11/404
CPC分类号： G11C11/4096 , G11C11/4045
摘要： The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive a first one of the access lines to a read/program voltage through the two-transistor driver, during a PULSE phase and drive a second one of the access lines physically adjacent to the first one of the access lines to a shielding voltage through the two-transistor driver, during the PULSE phase.
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公开(公告)号：US20240212736A1
公开(公告)日：2024-06-27
申请号：US18528451
申请日：2023-12-04
IPC分类号： G11C11/22 , G11C11/408 , G11C11/4091
CPC分类号： G11C11/2257 , G11C11/2273 , G11C11/4085 , G11C11/4091
摘要： Methods, systems, and devices for word line charge integration are described. In some examples, a memory device may include a plurality of memory cells that are coupled with a word line and respective digit lines. During a read operation, the word line may be activated (e.g., driven to a voltage) and a subset of the respective digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of each of the memory cells. Before each digit line is activated, the word line may be deactivated and the remaining digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of the remaining memory cells that are coupled with the word line. After each of the digit lines are selected, respective sense components may be activated to sense the charges associated with the memory cells.
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公开(公告)号：US20240177792A1
公开(公告)日：2024-05-30
申请号：US18521891
申请日：2023-11-28
CPC分类号： G11C29/46 , G11C29/1201 , G11C29/42
摘要： Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:
storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.-
公开(公告)号：US20240071489A1
公开(公告)日：2024-02-29
申请号：US17896963
申请日：2022-08-26
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0038 , G11C2213/79
摘要： Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.
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公开(公告)号：US11901029B2
公开(公告)日：2024-02-13
申请号：US18112307
申请日：2023-02-21
CPC分类号： G11C29/42 , G11C7/14 , G11C29/12005 , G11C29/20 , G11C29/44
摘要： Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
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公开(公告)号：US11900989B2
公开(公告)日：2024-02-13
申请号：US17370488
申请日：2021-07-08
IPC分类号： G11C11/40 , G11C11/4096 , G11C11/4091 , G11C11/408 , H10B12/00 , G11C11/56
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4091 , H10B12/30 , H10B12/50 , G11C11/4087 , G11C11/565
摘要： Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
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公开(公告)号：US20240038322A1
公开(公告)日：2024-02-01
申请号：US17873991
申请日：2022-07-26
发明人： Michele Maria Venturini , Umberto Di Vincenzo , Ferdinando Bedeschi , Riccardo Muzzetto , Christophe Vincent Antoine Laurent , Christian Caillat
IPC分类号： G11C29/50
CPC分类号： G11C29/50004 , G11C2029/5004
摘要： Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.
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公开(公告)号：US20230395136A1
公开(公告)日：2023-12-07
申请号：US18196268
申请日：2023-05-11
发明人： Andrea Martinelli , Claudia Palattella , Christophe Vincent Antoine Laurent , Ferdinando Bedeschi , Efrem Bolandrina
IPC分类号： G11C11/4096 , G11C11/4078 , G11C11/4099
CPC分类号： G11C11/4096 , G11C11/4078 , G11C11/4099
摘要： Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.
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公开(公告)号：US20230395135A1
公开(公告)日：2023-12-07
申请号：US17864046
申请日：2022-07-13
IPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4093 , G11C11/4076
CPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4093 , G11C11/4076
摘要： Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.
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10.发明授权公开(公告)号：US11776590B2
公开(公告)日：2023-10-03
申请号：US17748866
申请日：2022-05-19
CPC分类号： G11C7/1009 , G11C7/06 , G11C7/1012 , G11C16/10 , G11C16/26 , G11C29/42
摘要： The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.
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