Invention Grant
- Patent Title: Logic circuit block layouts with dual-side processing
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Application No.: US15387501Application Date: 2016-12-21
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Publication No.: US10083963B2Publication Date: 2018-09-25
- Inventor: Sinan Goktepeli , Jean Richaud
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Seyfarth Shaw LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L29/06 ; H01L29/423 ; H01L21/768 ; H01L21/822 ; H01L27/06

Abstract:
An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor.
Public/Granted literature
- US20180175034A1 LOGIC CIRCUIT BLOCK LAYOUTS WITH DUAL-SIDE PROCESSING Public/Granted day:2018-06-21
Information query
IPC分类: