Invention Grant
- Patent Title: Multiple instruction issuance with parallel inter-group and intra-group picking
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Application No.: US15086052Application Date: 2016-03-30
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Publication No.: US10089114B2Publication Date: 2018-10-02
- Inventor: Milind Ram Kulkarni , Rami Mohammad A. Al Sheikh , Raguram Damodaran
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C./QUALCOMM
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30

Abstract:
A scheduler with a picker block capable of dispatching multiple instructions per cycle is disclosed. The picker block may comprise an inter-group picker and an intra-group picker. The inter-group picker may be configured to pick multiple ready groups when there are two or more ready groups among a plurality of groups of instructions, and pick a single ready group when the single ready group is the only ready group among the plurality of groups. The intra-group picker may be configured to pick one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and to pick multiple ready instructions from the single ready group when the inter-group picker picks the single ready group.
Public/Granted literature
- US20170286120A1 APPARATUS AND METHOD TO MAXIMIZE EXECUTION LANE UTILIZATION THROUGH A CUSTOM HIGH THROUGHPUT SCHEDULER Public/Granted day:2017-10-05
Information query