公开(公告)号：US20180081691A1

公开(公告)日：2018-03-22

申请号：US15271366

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  Rami Mohammad Al Sheikh ,  Raguram Damodaran

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: Replaying speculatively dispatched load-dependent instructions in response to a cache miss for a producing load instruction in an out-of-order processor (OoP) is disclosed. To allow for a scheduler circuit to restore register dependencies in a register dependency tracking circuit for a replay operation in response to a cache miss for execution of a load instruction, the scheduler circuit includes a replay circuit. The replay circuit includes a load dependency tracking circuit. The replay circuit is configured to track dependencies of dispatched load instructions in the load dependency tracking circuit. The replay circuit uses these tracked dependencies to restore register dependencies for the dispatched load instructions in the register dependency tracking circuit in response to a replay operation. Thus, the load instruction does not have to be re-allocated to restore register dependencies in the register dependency tracking circuit used for re-dispatching load-dependent instructions.

公开(公告)号：US20170277536A1

公开(公告)日：2017-09-28

申请号：US15079875

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Vignyan Reddy Kothinti Naresh ,  Shivam Priyadarshi ,  Raguram Damodaran

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867

Abstract: Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor is disclosed herein. In one aspect, a low resource micro-operation controller is provided. Responsive to an instruction pipeline receiving an instruction address, the low resource micro-operation controller is configured to determine if the received instruction address corresponds to an instruction address in short history table. Short history table includes instruction addresses of recently-provided instructions having micro-ops in a post-decode queue. If the received instruction address corresponds to an instruction address in short history table, the low resource micro-operation controller is configured to provide reference (e.g., pointer) to the fetch stage that corresponds to an entry in the post-decode queue in which the micro-ops corresponding to the instruction address are stored. Responsive to the decode stage receiving the reference, the low resource micro-operation controller is configured to provide the micro-ops from the post-decode queue for execution.

公开(公告)号：US20170177366A1

公开(公告)日：2017-06-22

申请号：US14977840

申请日：2015-12-22

Applicant: QUALCOMM Incorporated

Inventor： Vignyan Reddy Kothinti Naresh ,  Shivam Priyadarshi ,  Raguram Damodaran

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867

Abstract: Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor is disclosed. In one aspect, a selective instruction sequence buffer controller is configured to selectively store previously decoded instructions for an instruction sequence by determining if a received instruction address corresponds to an instruction sequence captured in an instruction sequence buffer. If the received instruction address corresponds to a captured instruction sequence, the selective instruction sequence buffer controller provides corresponding micro-operations stored in the instruction sequence buffer for execution. If the received instruction address does not correspond to the captured instruction sequence, the selective instruction sequence buffer controller reduces a frequency indicator of the instruction sequence. The selective instruction sequence buffer controller may also increase the frequency indicator of the instruction sequence when the instruction sequence is accessed, capturing the instruction sequence once the frequency indicator meets a threshold.

公开(公告)号：US09582285B2

公开(公告)日：2017-02-28

申请号：US14223091

申请日：2014-03-24

Applicant: QUALCOMM Incorporated

Inventor： Rami Mohammad Al Sheikh ,  Raguram Damodaran

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3844

Abstract: Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media are disclosed. In one embodiment, a branch prediction circuit including a first branch predictor and a second branch predictor is provided. The first branch predictor generates a first branch prediction for a conditional branch instruction, and the first branch prediction is stored in a first branch prediction history. The first branch prediction is also speculatively forwarded to a second branch prediction history. The second branch predictor subsequently generates a second branch prediction based on the second branch prediction history, including the speculatively forwarded first branch prediction. By enabling the second branch predictor to base its branch prediction on the speculatively forwarded first branch prediction, an accuracy of the second branch predictor may be improved.

Abstract translation: 公开了覆盖分支预测器以及相关电路，方法和计算机可读介质中的投机历史转发。 在一个实施例中，提供了包括第一分支预测器和第二分支预测器的分支预测电路。 第一分支预测器产生用于条件分支指令的第一分支预测，并且第一分支预测存储在第一分支预测历史中。 第一分支预测也被推测地转发到第二分支预测历史。 第二分支预测器随后基于包括推测性转发的第一分支预测的第二分支预测历史生成第二分支预测。 通过使第二分支预测器能够将其分支预测设置在推测性转发的第一分支预测上，可以提高第二分支预测器的精度。

公开(公告)号：US10551896B2

公开(公告)日：2020-02-04

申请号：US15814361

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran ,  Jeffrey Todd Bridges ,  Ryan Wells ,  Norman Gargash ,  Rodney Wayne Smith

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US10474462B2

公开(公告)日：2019-11-12

申请号：US15057116

申请日：2016-02-29

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Rami Mohammad Al Sheikh ,  Raguram Damodaran ,  Michael Scott McIlvaine ,  Jeffrey Todd Bridges

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems and methods for operating a processor include determining confidence levels, such as high, low, and medium confidence levels, associated with in-flight branch instructions in an instruction pipeline of the processor, based on counters used for predicting directions of the in-flight branch instructions. Numbers of in-flight branch instructions associated with each of confidence levels are determined. A weighted sum of the numbers weighted with weights corresponding to the confidence levels is calculated and the weighted sum is compared with a threshold. A throttling signal may be asserted to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.

公开(公告)号：US10089114B2

公开(公告)日：2018-10-02

申请号：US15086052

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  Rami Mohammad A. Al Sheikh ,  Raguram Damodaran

IPC: G06F9/38 ,  G06F9/30

Abstract: A scheduler with a picker block capable of dispatching multiple instructions per cycle is disclosed. The picker block may comprise an inter-group picker and an intra-group picker. The inter-group picker may be configured to pick multiple ready groups when there are two or more ready groups among a plurality of groups of instructions, and pick a single ready group when the single ready group is the only ready group among the plurality of groups. The intra-group picker may be configured to pick one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and to pick multiple ready instructions from the single ready group when the inter-group picker picks the single ready group.

公开(公告)号：US09830152B2

公开(公告)日：2017-11-28

申请号：US14977840

申请日：2015-12-22

Applicant: QUALCOMM Incorporated

Inventor： Vignyan Reddy Kothinti Naresh ,  Shivam Priyadarshi ,  Raguram Damodaran

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867

Abstract: Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor is disclosed. In one aspect, a selective instruction sequence buffer controller is configured to selectively store previously decoded instructions for an instruction sequence by determining if a received instruction address corresponds to an instruction sequence captured in an instruction sequence buffer. If the received instruction address corresponds to a captured instruction sequence, the selective instruction sequence buffer controller provides corresponding micro-operations stored in the instruction sequence buffer for execution. If the received instruction address does not correspond to the captured instruction sequence, the selective instruction sequence buffer controller reduces a frequency indicator of the instruction sequence. The selective instruction sequence buffer controller may also increase the frequency indicator of the instruction sequence when the instruction sequence is accessed, capturing the instruction sequence once the frequency indicator meets a threshold.

公开(公告)号：US20170046154A1

公开(公告)日：2017-02-16

申请号：US14860032

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Rodney Wayne Smith ,  Sandeep Suresh Navada ,  Shivam Priyadarshi ,  Raguram Damodaran

IPC: G06F9/30

CPC classification number: G06F9/30112 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor (OoP) is provided. An OoP is provided that includes an instruction processing system. The instruction processing system includes a number of instruction processing stages configured to pipeline the processing and execution of instructions according to a dataflow execution. The instruction processing system also includes a register map table (RMT) configured to store address pointers mapping logical registers to physical registers in a physical register file (PRF) for storing produced data for use by consumer instructions without overwriting logical registers for later executed, out-of-order instructions. In certain aspects, the instruction processing system is configured to write back (i.e., store) narrow values produced by executed instructions directly into the RMT, as opposed to writing the narrow produced values into the PRF in a write back stage.

Abstract translation: 提供将指令操作数的窄生成值直接存储在乱序处理器（OoP）的寄存器映射中。 提供了包括指令处理系统的OoP。 指令处理系统包括多个指令处理阶段，其被配置为根据数据流执行流水线处理和执行指令。 指令处理系统还包括寄存器映射表（RMT），其被配置为存储将逻辑寄存器映射到物理寄存器文件（PRF）中的物理寄存器的地址指针，用于存储由消费者指令使用的产生数据，而不覆盖用于稍后执行的逻辑寄存器 订单说明。 在某些方面，指令处理系统被配置为将由执行的指令产生的窄值直接写入（即存储）到RMT中，而不是在写回阶段将窄的产生值写入PRF。

公开(公告)号：US11709679B2

公开(公告)日：2023-07-25

申请号：US15087069

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Rami Mohammad Al Sheikh ,  Raguram Damodaran

IPC: G06F9/38

CPC classification number: G06F9/3832

Abstract: Aspects disclosed in the detailed description include providing load address predictions using address prediction tables based on load path history in processor-based systems. In one aspect, a load address prediction engine provides a load address prediction table containing multiple load address prediction table entries. Each load address prediction table entry includes a predictor tag field and a memory address field for a load instruction. The load address prediction engine generates a table index and a predictor tag based on an identifier and a load path history for a detected load instruction. The table index is used to look up a corresponding load address prediction table entry. If the predictor tag matches the predictor tag field of the load address prediction table entry corresponding to the table index, the memory address field of the load address prediction table entry is provided as a predicted memory address for the load instruction.