公开(公告)号：US10089114B2

公开(公告)日：2018-10-02

申请号：US15086052

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  Rami Mohammad A. Al Sheikh ,  Raguram Damodaran

IPC: G06F9/38 ,  G06F9/30

Abstract: A scheduler with a picker block capable of dispatching multiple instructions per cycle is disclosed. The picker block may comprise an inter-group picker and an intra-group picker. The inter-group picker may be configured to pick multiple ready groups when there are two or more ready groups among a plurality of groups of instructions, and pick a single ready group when the single ready group is the only ready group among the plurality of groups. The intra-group picker may be configured to pick one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and to pick multiple ready instructions from the single ready group when the inter-group picker picks the single ready group.

公开(公告)号：US20170053685A1

公开(公告)日：2017-02-23

申请号：US15087219

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  David Paul Hoff

IPC: G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

Abstract translation: 公开了一种用于激活用于存储器访问操作的存储器中的多个存储器位置的存储器系统中的多热（多热）位解码。 一方面，提供一种多热位解码系统，其包括包括解码器的存储器访问控制系统。 解码器被配置为将用于存储器访问操作的地址解码为用于激活编码地址处的存储器行的单个热位解码字。 为了自动访问用于存储器访问操作的另一存储器行，存储器访问控制系统还包括映射电路，其被配置为基于该地址提供用于激活另一个存储器行的附加解码字。 合并解码字和附加解码字以提供被断言在解码字线上的多位热解码字，使得多个存储器行被激活用于存储器访问操作。

公开(公告)号：US20180081691A1

公开(公告)日：2018-03-22

申请号：US15271366

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  Rami Mohammad Al Sheikh ,  Raguram Damodaran

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3838 ,  G06F9/3842 ,  G06F9/3863

Abstract: Replaying speculatively dispatched load-dependent instructions in response to a cache miss for a producing load instruction in an out-of-order processor (OoP) is disclosed. To allow for a scheduler circuit to restore register dependencies in a register dependency tracking circuit for a replay operation in response to a cache miss for execution of a load instruction, the scheduler circuit includes a replay circuit. The replay circuit includes a load dependency tracking circuit. The replay circuit is configured to track dependencies of dispatched load instructions in the load dependency tracking circuit. The replay circuit uses these tracked dependencies to restore register dependencies for the dispatched load instructions in the register dependency tracking circuit in response to a replay operation. Thus, the load instruction does not have to be re-allocated to restore register dependencies in the register dependency tracking circuit used for re-dispatching load-dependent instructions.

公开(公告)号：US09830965B2

公开(公告)日：2017-11-28

申请号：US15087219

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  David Paul Hoff

IPC: G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

公开(公告)号：US10203745B2

公开(公告)日：2019-02-12

申请号：US15086049

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  Rami Mohammad A. Al Sheikh ,  Raguram Damodaran

IPC: G06F1/32 ,  G06F9/38

Abstract: A scheduler and method for dynamic power reduction, e.g., in a processor core, is proposed. In conventional processor cores for example, the scheduler precharges grant lines of many instructions only to discharge a great majority of the precharged lines in one cycle. To reduce power consumption, selective precharge and/or selective evaluation are proposed. In the selective precharge, the grant lines of instructions that will evaluate to false (e.g., invalid instructions) are not precharged in a cycle. In the selective evaluation, among the precharged instructions, instructions that are not ready are not evaluated in the same cycle. In this way, power consumption is reduced by avoiding unnecessary precharge and discharge.

公开(公告)号：US09852080B2

公开(公告)日：2017-12-26

申请号：US15087077

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Milind Ram Kulkarni ,  Benjamin John Bowers

IPC: G06F12/10 ,  G06F12/0879 ,  G06F12/0895 ,  G06F1/06 ,  G06F12/14 ,  G06F12/1027

CPC classification number: G06F12/10 ,  G06F1/06 ,  G06F12/0879 ,  G06F12/0895 ,  G06F12/1027 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/65

Abstract: Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

公开(公告)号：US20170052900A1

公开(公告)日：2017-02-23

申请号：US15087077

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Milind Ram Kulkarni ,  Benjamin John Bowers

IPC: G06F12/10 ,  G06F1/06

CPC classification number: G06F12/10 ,  G06F1/06 ,  G06F12/0879 ,  G06F12/0895 ,  G06F12/1027 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/65

Abstract: Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

Abstract translation: 公开了在索引的地址空间内高效地生成用于行选择的选择掩码。 在这方面，在一个方面，提供了一种索引阵列电路，包括指示行选择的开始索引的数组行的开始指示符和指示行选择的结束索引的数组行的结束指示符。 索引阵列电路还包括以逻辑序列排序的多个索引阵列行，每个包括行级比较电路。 每个行级比较电路被配置为基于索引数组行的逻辑地址的位的子集与开始指示符的相应的子集的第一并行比较来生成选择掩码指示符，以及子集的第二并行比较 的索引数组行的逻辑地址的位与终端指示符的相应的子集。