- Patent Title: Error detection constants of symbol transition clocking transcoding
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Application No.: US14949435Application Date: 2015-11-23
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Publication No.: US10089173B2Publication Date: 2018-10-02
- Inventor: Shoichiro Sengoku
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00 ; H03M13/03 ; H03M5/00 ; H04L1/00 ; H04L25/02 ; H04L25/03 ; H04L25/14 ; H04L25/493 ; H04L27/38 ; H04L1/24 ; H04L7/033

Abstract:
Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.
Public/Granted literature
- US20160147596A1 ERROR DETECTION CONSTANTS OF SYMBOL TRANSITION CLOCKING TRANSCODING Public/Granted day:2016-05-26
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