Invention Grant
- Patent Title: Substrate, semiconductor package structure and manufacturing process
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Application No.: US15439752Application Date: 2017-02-22
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Publication No.: US10096542B2Publication Date: 2018-10-09
- Inventor: Chih Cheng Lee , Yuan-Chang Su
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/31 ; H01L21/48 ; H01L21/683 ; H01L23/00

Abstract:
A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.
Public/Granted literature
- US20180240743A1 SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING PROCESS Public/Granted day:2018-08-23
Information query
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