公开(公告)号：US10748843B2

公开(公告)日：2020-08-18

申请号：US15356407

申请日：2016-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Po-Shu Peng ,  Cheng-Lin Ho ,  Chih Cheng Lee

IPC: H05K1/18 ,  H01L23/498 ,  H05K3/46 ,  H01L21/48

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers. At least one of the patterned conductive layers is located at a depth spanning between a top surface of the passive layer and a bottom surface of the component

公开(公告)号：US10340212B2

公开(公告)日：2019-07-02

申请号：US15824913

申请日：2017-11-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee ,  Yu-Lin Shih

IPC: H01L23/49 ,  H01L23/36 ,  H01L23/495 ,  H01L23/42 ,  H01L23/367 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface. The heat dissipation structure is surrounded by the dielectric layer. The heat dissipation structure defines a space and includes a liquid in the space. The first patterned conductive layer is disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.

公开(公告)号：US10424547B2

公开(公告)日：2019-09-24

申请号：US15691053

申请日：2017-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee ,  Yuan-Chang Su

IPC: H05K1/03 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H05K1/02

Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.

公开(公告)号：US10096542B2

公开(公告)日：2018-10-09

申请号：US15439752

申请日：2017-02-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee ,  Yuan-Chang Su

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.

公开(公告)号：US10074602B2

公开(公告)日：2018-09-11

申请号：US15349954

申请日：2016-11-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A substrate includes a first conductive structure, a second conductive structure attached to the first conductive structure and a third conductive structure attached to the second conductive structure. The first conductive structure includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer. The second conductive structure includes at least one second dielectric layer disposed on a second surface of the first dielectric layer and at least one second circuit layer embedded in the second dielectric layer. The third conductive structure includes a third dielectric layer disposed on the second conductive structure and a third circuit layer disposed on the third dielectric layer. A material of the second dielectric layer is different from the a material of the first dielectric layer and a material of the third dielectric layer.

公开(公告)号：US11715694B2

公开(公告)日：2023-08-01

申请号：US17373532

申请日：2021-07-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsing Kuo Tien ,  Chih Cheng Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5384

Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US11232993B2

公开(公告)日：2022-01-25

申请号：US16402127

申请日：2019-05-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih Cheng Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device package includes a dielectric layer, a package body and a protection structure. The dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The package body is disposed on the first surface of the dielectric layer. The package body covers a first portion of the lateral surface of the dielectric layer and exposes a second portion of the lateral surface of the dielectric layer. The protection structure is disposed on the second portion of the lateral surface of the dielectric layer.

公开(公告)号：US20180138114A1

公开(公告)日：2018-05-17

申请号：US15349954

申请日：2016-11-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A substrate includes a first conductive structure, a second conductive structure attached to the first conductive structure and a third conductive structure attached to the second conductive structure. The first conductive structure includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer. The second conductive structure includes at least one second dielectric layer disposed on a second surface of the first dielectric layer and at least one second circuit layer embedded in the second dielectric layer. The third conductive structure includes a third dielectric layer disposed on the second conductive structure and a third circuit layer disposed on the third dielectric layer. A material of the second dielectric layer is different from the a material of the first dielectric layer and a material of the third dielectric layer.

公开(公告)号：US09887167B1

公开(公告)日：2018-02-06

申请号：US15269787

申请日：2016-09-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee ,  Hsing Kuo Tien ,  Li Chuan Tsai

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/29191 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A package structure includes a carrier defining a cavity in which a die is disposed. A dielectric material fills the cavity around the die. A first conductive layer is disposed over a first surface of the carrier. A first dielectric layer is disposed over an active surface of the die, the first conductive layer and the first surface of the carrier. A first conductive pattern is disposed over the first dielectric layer, and is electrically connected to the first conductive layer and to the active surface of the die. A second dielectric layer is disposed over the second surface of the carrier and defines a hole having a wall aligned with a sidewall of the cavity. A second conductive layer is disposed over the second dielectric layer. A third conductive layer is disposed on the sidewall of the cavity and the wall of the second dielectric layer.

公开(公告)号：US11276660B2

公开(公告)日：2022-03-15

申请号：US16698671

申请日：2019-11-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor device package includes an electronic component, a first passivation layer having an inner surface surrounding the electronic component, and a conductive layer disposed on the inner surface of the first passivation layer. The electronic component has a first surface, a second surface opposite the first surface, and a lateral surface extended between the first surface and the second surface. The conductive layer has a relatively rough surface. A method of manufacturing a semiconductor device package is also disclosed.