Invention Grant
- Patent Title: Integrated circuit layout wiring for multi-core chips
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Application No.: US14985887Application Date: 2015-12-31
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Publication No.: US10097182B2Publication Date: 2018-10-09
- Inventor: Chetan Bisht , Harry Scrivener, III
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMICROELECTRONICS, INC.
- Current Assignee: STMICROELECTRONICS, INC.
- Current Assignee Address: US TX Coppell
- Agency: Seed IP Law Group LLP
- Main IPC: H03K19/0175
- IPC: H03K19/0175 ; H01L23/528 ; H01L23/50 ; G06F17/50

Abstract:
An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
Public/Granted literature
- US20160191058A1 INTEGRATED CIRCUIT LAYOUT WIRING FOR MULTI-CORE CHIPS Public/Granted day:2016-06-30
Information query
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