公开(公告)号：US10812079B2

公开(公告)日：2020-10-20

申请号：US16142627

申请日：2018-09-26

Applicant: STMicroelectronics, Inc.

Inventor： Chetan Bisht ,  Harry Scrivener, III

IPC: H03K19/0175 ,  H01L23/528 ,  H01L23/50 ,  G06F17/50

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

公开(公告)号：US10102327B2

公开(公告)日：2018-10-16

申请号：US14871584

申请日：2015-09-30

Applicant: STMicroelectronics, Inc.

Inventor： Chetan Bisht ,  Harry Scrivener, III

IPC: G06F17/50 ,  H03K19/0175 ,  H03F3/195 ,  H03F3/60

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

公开(公告)号：US20160188777A1

公开(公告)日：2016-06-30

申请号：US14871584

申请日：2015-09-30

Applicant: STMicroelectronics, Inc.

Inventor： Chetan Bisht ,  Harry Scrivener, III

IPC: G06F17/50 ,  H03K19/0175

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H03F3/195 ,  H03F3/602 ,  H03K19/017509

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract translation: 集成电路片上系统（SOC）包括半导体衬底，由形成在衬底中的晶体管构成的多个部件，以及在组件之间提供电连接的多个互连线。 使用无通道设计消除了芯片顶表面上的互连通道。 相反，互连线在金属化的顶层中彼此邻接，从而保留了5-10％的芯片不动产。 通常沿组件之间的互连通道定位的时钟缓冲器位于包含组件的衬底的区域内。 无通道集成电路的设计规则允许馈通互连并排除多扇出互连。

公开(公告)号：US10747933B2

公开(公告)日：2020-08-18

申请号：US16160780

申请日：2018-10-15

Applicant: STMicroelectronics, Inc.

Inventor： Chetan Bisht ,  Harry Scrivener, III

IPC: G06F30/394 ,  H03K19/0175 ,  G06F30/392 ,  H03F3/195 ,  H03F3/60

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

公开(公告)号：US10097182B2

公开(公告)日：2018-10-09

申请号：US14985887

申请日：2015-12-31

Applicant: STMicroelectronics, Inc.

Inventor： Chetan Bisht ,  Harry Scrivener, III

IPC: H03K19/0175 ,  H01L23/528 ,  H01L23/50 ,  G06F17/50

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.