Invention Grant
- Patent Title: Manufacturing process of element chip
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Application No.: US15811733Application Date: 2017-11-14
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Publication No.: US10147646B2Publication Date: 2018-12-04
- Inventor: Hidehiko Karasaki , Hidefumi Saeki , Atsushi Harikai
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JP2016-243325 20161215
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/268

Abstract:
A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.
Public/Granted literature
- US20180174908A1 MANUFACTURING PROCESS OF ELEMENT CHIP Public/Granted day:2018-06-21
Information query
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