Invention Grant
- Patent Title: Scoreboard approach to managing idle page close timeout duration in memory
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Application No.: US15477069Application Date: 2017-04-01
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Publication No.: US10176124B2Publication Date: 2019-01-08
- Inventor: Sriseshan Srikanth , Lavanya Subramanian , Sreenivas Subramoney
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Thorpe North & Western, LLP
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/40 ; G06F9/38 ; G11C7/10 ; G11C7/22

Abstract:
A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.
Public/Granted literature
- US20180285286A1 SCOREBOARD APPROACH TO MANAGING IDLE PAGE CLOSE TIMEOUT DURATION IN MEMORY Public/Granted day:2018-10-04
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