Invention Grant
- Patent Title: Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit
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Application No.: US15596767Application Date: 2017-05-16
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Publication No.: US10177101B2Publication Date: 2019-01-08
- Inventor: Christian Rivero , Pascal Fornara , Guilhem Bouton , Mathieu Lisart
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1661347 20161122
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/311 ; H01L23/528 ; H01L27/088 ; H01L23/522 ; H01L23/58 ; H01L21/768

Abstract:
An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
Public/Granted literature
Information query
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