A gate driving circuit sequentially outputting a gate voltage using a high level power voltage, a low level power voltage, a start voltage, a previous stage gate voltage, a next stage gate voltage and a clock, includes: a shift register including a plurality of stages connected to each other by a cascade connection, each of the plurality of stages including: a first thin film transistor (TFT) switched by the start voltage or the previous stage gate voltage and transmitting the high level power voltage to a Q node; a second TFT switched by the next stage gate voltage and transmitting the low level power voltage to the Q node; a third TFT switched by a voltage of the Q node and transmitting the clock to an output node; and a first resistor connected between the output node and the low level power voltage.