公开(公告)号：US20160171915A1

公开(公告)日：2016-06-16

申请号：US14872773

申请日：2015-10-01

Applicant: LG Display Co., Ltd.

Inventor： Ju-Young Lee ,  Seung-Wan Cho

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0871 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2330/04 ,  G11C19/28

Abstract: A gate driving circuit sequentially outputting a gate voltage using a high level power voltage, a low level power voltage, a start voltage, a previous stage gate voltage, a next stage gate voltage and a clock, includes: a shift register including a plurality of stages connected to each other by a cascade connection, each of the plurality of stages including: a first thin film transistor (TFT) switched by the start voltage or the previous stage gate voltage and transmitting the high level power voltage to a Q node; a second TFT switched by the next stage gate voltage and transmitting the low level power voltage to the Q node; a third TFT switched by a voltage of the Q node and transmitting the clock to an output node; and a first resistor connected between the output node and the low level power voltage.

Abstract translation: 栅极驱动电路使用高电平电源电压，低电平电源电压，起始电压，前一级栅极电压，下一级栅极电压和时钟顺序地输出栅极电压，包括：移位寄存器，包括多个 通过级联连接彼此连接的级，所述多级中的每一级包括：通过所述启动电压或所述前级栅极电压切换的第一薄膜晶体管（TFT），并将所述高电平电源电压传输到Q节点; 通过下一级栅极电压切换的第二TFT，并将低电平电源电压传输到Q节点; 通过Q节点的电压切换的第三TFT，并将时钟传送到输出节点; 以及连接在输出节点和低电平电源电压之间的第一电阻器。

公开(公告)号：US10181276B2

公开(公告)日：2019-01-15

申请号：US14872773

申请日：2015-10-01

Applicant: LG Display Co., Ltd.

Inventor： Ju-Young Lee ,  Seung-Wan Cho

IPC: G09G3/36 ,  G11C27/04 ,  G09G3/20 ,  G09G3/3266 ,  G11C19/28

Abstract: A gate driving circuit sequentially outputting a gate voltage using a high level power voltage, a low level power voltage, a start voltage, a previous stage gate voltage, a next stage gate voltage and a clock, includes: a shift register including a plurality of stages connected to each other by a cascade connection, each of the plurality of stages including: a first thin film transistor (TFT) switched by the start voltage or the previous stage gate voltage and transmitting the high level power voltage to a Q node; a second TFT switched by the next stage gate voltage and transmitting the low level power voltage to the Q node; a third TFT switched by a voltage of the Q node and transmitting the clock to an output node; and a first resistor connected between the output node and the low level power voltage.