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    Sequencing biopolymers
    3.
    发明授权
    Sequencing biopolymers 有权

    公开(公告)号：US10822654B2

    公开(公告)日：2020-11-03

    申请号：US14910990

    申请日：2014-05-08

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Walter Gumbrecht ,  Oliver Hayden ,  Meinrad Schienle

    IPC分类号： G01N33/48 ,  G01N33/50 ,  C12Q1/6874 ,  G01N33/487 ,  G11C27/04 ,  G11C13/00 ,  G11C19/00 ,  C12Q1/6869

    摘要： The invention relates to a method and a corresponding arrangement for sequencing at least two biopolymers (6), wherein for each biopolymer (6) a sequence signal is picked up by a respective measured variable pickup on the basis of the sequence of the biopolymer (6), the sequence signals are transferred to a shift register (16) and buffer-stored therein, the buffer-stored sequence signals are transferred from the shift register (16) sequentially to an evaluation device (26) and evaluated therein. Each sequence signal is preferably produced here by means of a nanopore arrangement (10). A corresponding sequencing arrangement (11) has the measured variable pickups and the shift register (16) integrated in it, preferably in an electrical circuit, that is to say on a sensor array, for example. Each sequence signal can be amplified here by a preamplifier (14) prior to transfer to the shift register (16). The transfer of the output signal (A) to the evaluation device (24) can comprise the amplification of the signal by an output amplifier (24) and/or at least one EMCCD stage (32).

    SCANNING-LINE DRIVE CIRCUIT
    5.
    发明申请
    SCANNING-LINE DRIVE CIRCUIT 审中-公开

    公开(公告)号：US20170110077A1

    公开(公告)日：2017-04-20

    申请号：US15395547

    申请日：2016-12-30

    申请人： MITSUBISHI ELECTRIC CORPORATION

    发明人： Youichi TOBITA

    IPC分类号： G09G3/36 ,  G11C27/04

    摘要： A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

    SHIFT REGISTER UNIT, DISPLAY PANEL AND DISPLAY DEVICE
    6.
    发明申请
    SHIFT REGISTER UNIT, DISPLAY PANEL AND DISPLAY DEVICE 审中-公开
    移位寄存器单元，显示面板和显示设备

    公开(公告)号：US20150016584A1

    公开(公告)日：2015-01-15

    申请号：US14226760

    申请日：2014-03-26

    申请人： Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC Optoelectronics Co., Ltd.

    发明人： Dongliang DUN ,  Zhiqiang XIA

    IPC分类号： G11C27/04

    CPC分类号： G11C27/04 ,  G09G3/3266 ,  G09G2310/0286 ,  G11C19/28

    摘要： A shift register unit, a display panel including the shift register unit and a display device including the display panel are provided. The shift register unit includes a driving module, an output module, a first transistor, and a second transistor. By connecting a second electrode of the first transistor in the shift register unit with an output terminal of the shift register unit, even if a channel width of the second transistor is considerably smaller than a theoretical design value, abnormal output of the shift register unit can be avoided.

    摘要翻译： 提供了移位寄存器单元，包括移位寄存器单元的显示面板和包括显示面板的显示设备。 移位寄存器单元包括驱动模块，输出模块，第一晶体管和第二晶体管。 通过将移位寄存器单元中的第一晶体管的第二电极与移位寄存器单元的输出端子连接，即使第二晶体管的沟道宽度明显小于理论设计值，移位寄存器单元的异常输出也可以 避免。

    STAGE CIRCUIT AND SCAN DRIVER USING THE SAME
    7.
    发明申请
    STAGE CIRCUIT AND SCAN DRIVER USING THE SAME 有权
    阶段电路和扫描驱动器使用它

    公开(公告)号：US20140355733A1

    公开(公告)日：2014-12-04

    申请号：US14276980

    申请日：2014-05-13

    申请人： SAMSUNG DISPLAY CO., LTD.

    发明人： Yong-Jae Kim ,  Dong-Gyu Kim ,  Sung-Jae Moon

    IPC分类号： G09G3/32 ,  G11C27/04

    CPC分类号： G09G3/3266 ,  G09G2310/0205 ,  G09G2310/0286 ,  G11C19/28

    摘要： A stage circuit and a scan driver, the stage circuit including a switch unit configured to selectively electrically couple a first node to one of a first input terminal and a second input terminal, a first driver coupled to the first node, to a second node, to a third node, to a first clock terminal, and to a second clock terminal, and a second driver coupled to the second node, to the third node, to a third clock terminal, and to a common terminal, and configured to output a scan signal to an output terminal.

    摘要翻译： 舞台电路和扫描驱动器，舞台电路包括被配置为选择性地将第一节点电耦合到第一输入端和第二输入端之一的开关单元，耦合到第一节点的第一驱动器，第二节点， 到第三节点，连接到第一时钟终端，以及耦合到第二节点的第二时钟终端和耦合到第三节点的第二驱动器，连接到第三时钟终端，并且被配置为输出 扫描信号到输出端。

    Command latency systems and methods
    8.
    发明授权
    Command latency systems and methods 有权
    命令延迟系统和方法

    公开(公告)号：US08773928B2

    公开(公告)日：2014-07-08

    申请号：US13915351

    申请日：2013-06-11

    申请人： Micron Technology, Inc.

    发明人： Donald M. Morgan

    IPC分类号： G11C27/04

    CPC分类号： G11C8/18 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C2207/2272 ,  H03H11/26

    摘要： Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required.

    摘要翻译： 描述了命令延迟系统和方法的示例。 在一些示例中，存储与接收到的命令信号相关联的相位信息，接收的命令信号通过减法时钟触发器流水线传播，并且延迟的命令信号与存储的相位信息组合。 缩小时钟触发器管线可以使用具有比用于发出命令信号的频率更低的频率的时钟。 因此，可能需要较少的触发器。

    Clock generation circuit for analog value memory circuit
    10.
    发明授权
    Clock generation circuit for analog value memory circuit 失效
    模拟值存储电路的时钟发生电路

    公开(公告)号：US5999462A

    公开(公告)日：1999-12-07

    申请号：US205200

    申请日：1998-12-04

    申请人： Masayuki Katakura ,  Masashi Takeda

    发明人： Masayuki Katakura ,  Masashi Takeda

    IPC分类号： G11C7/22 ,  G11C27/04 ,  G11C7/00

    CPC分类号： G11C7/222 ,  G11C27/04 ,  G11C7/22

    摘要： An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

    摘要翻译： 一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 将X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数设置为除了1以外没有公共除数。因此，当要选择性地扫描存储器单元时， 可以在不依赖于存储单元的位置的情况下向所有存储单元提供相同的选择条件，并且减少连接到信号写/读终端的寄生电容。