Invention Grant
- Patent Title: Method for manufacturing semiconductor device, semiconductor mounting device, and memory device manufactured by method for manufacturing semiconductor device
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Application No.: US15562501Application Date: 2016-03-29
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Publication No.: US10181460B2Publication Date: 2019-01-15
- Inventor: Noboru Asahi , Yoshiyuki Arai , Yoshinori Miyamoto , Shimpei Aoki , Masatsugu Nimura
- Applicant: TORAY ENGINEERING CO., LTD.
- Applicant Address: JP Tokyo
- Assignee: TORAY ENGINEERING CO., LTD.
- Current Assignee: TORAY ENGINEERING CO., LTD.
- Current Assignee Address: JP Tokyo
- Agency: Global IP Counselors, LLP
- Priority: JP2015-069740 20150330
- International Application: PCT/JP2016/060079 WO 20160329
- International Announcement: WO2016/158935 WO 20161006
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/00 ; H01L21/78 ; H01L21/67 ; H01L23/00 ; H01L25/065 ; B28D5/02

Abstract:
A method for manufacturing a semiconductor device includes laminating a plurality of semiconductor wafers via an adhesive, heating such that the adhesive reaches a specific viscosity, and pressing the semiconductor wafers under a provisional pressure bonding load such that a gap between solder of through-electrodes provided to chip parts and through-electrodes of an adjacent semiconductor wafer falls within a specific range that is greater than zero, to produce a provisional pressure-bonded laminate; cutting the provisional pressure-bonded laminate with a cutter to produce a provisional pressure-bonded laminate chip part; and heating the provisional pressure-bonded laminate chip part to at least curing temperature of the adhesive and at least melting point of the solder, and pressing the provisional pressure-bonded laminate chip part under a main pressure bonding load to produce a main pressure-bonded laminate chip part such that the solder comes into contact with the through-electrodes of adjacent chip parts.
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