Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.