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    LOW SWING BITLINE FOR SENSING ARRAYS
    2.
    发明申请
    LOW SWING BITLINE FOR SENSING ARRAYS 审中-公开

    公开(公告)号：US20180294019A1

    公开(公告)日：2018-10-11

    申请号：US15485059

    申请日：2017-04-11

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C15/04

    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

    CURRENT STEERING LEVEL SHIFTER
    7.
    发明申请
    CURRENT STEERING LEVEL SHIFTER 有权
    电流转向水平仪

    公开(公告)号：US20160173092A1

    公开(公告)日：2016-06-16

    申请号：US14569569

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Carlos Tokunaga ,  James W. Tschanz

    IPC: H03K19/0175

    CPC classification number: H03K19/017509

    Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.

    Abstract translation: 描述了一种装置，其包括：第一电源节点，用于提供第一电源; 第二电源节点，用于提供第二电源; 驱动器在第一电源上运行，驱动器产生输出; 以及接收器，用于在所述第二电源上操作，所述接收器接收来自所述驱动器的输出并产生电平移位输出，使得所述接收器可操作以将电流从所述第二电源转向所述第一电源。

    Low swing bitline for sensing arrays
    9.
    发明授权
    Low swing bitline for sensing arrays 有权

    公开(公告)号：US10685688B2

    公开(公告)日：2020-06-16

    申请号：US16234065

    申请日：2018-12-27

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

    IPC: G11C7/00 ,  G11C7/12 ,  G11C11/419 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C15/04

    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

    Aging aware dynamic keeper apparatus and associated method
    10.
    发明授权
    Aging aware dynamic keeper apparatus and associated method 有权

    公开(公告)号：US10269419B2

    公开(公告)日：2019-04-23

    申请号：US15604519

    申请日：2017-05-24

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Vivek K. De ,  Muhammad M. Khellah

    IPC: G11C7/12 ,  G11C11/419

    Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.

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