Invention Grant
- Patent Title: Digital step attenuator with reduced relative phase error
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Application No.: US15256450Application Date: 2016-09-02
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Publication No.: US10205439B2Publication Date: 2019-02-12
- Inventor: Ravindranath Shrivastava , Kristian Madsen
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus LLP
- Agent Martin J. Jaquez, Esq.; Bruce W. Greenhaus, Esq.
- Main IPC: H03H11/24
- IPC: H03H11/24 ; H01F38/14

Abstract:
An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.
Public/Granted literature
- US20160373086A1 Digital Step Attenuator with Reduced Relative Phase Error Public/Granted day:2016-12-22
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