Invention Grant
- Patent Title: Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
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Application No.: US15864451Application Date: 2018-01-08
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Publication No.: US10211291B2Publication Date: 2019-02-19
- Inventor: Guilhem Bouton , Pascal Fornara , Christian Rivero
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1451616 20140228
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/78 ; H01L29/06 ; H01L21/762 ; H01L21/763 ; H01L27/112

Abstract:
An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
Public/Granted literature
Information query
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