- Patent Title: Memory expansion apparatus includes CPU-side protocol processor connected through parallel interface to memory-side protocol processor connected through serial link
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Application No.: US15194407Application Date: 2016-06-27
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Publication No.: US10216655B2Publication Date: 2019-02-26
- Inventor: Yong Seok Choi , Hyuk Je Kwon
- Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Applicant Address: KR Daejeon
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon
- Priority: KR10-2016-0025224 20160302
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/16 ; G06F13/40 ; G06F13/42 ; G06F12/0813
Abstract:
A memory interface apparatus is provided. The apparatus includes a central processing unit (CPU)-side protocol processor connected to a CPU through a parallel interface and a memory-side protocol processor connected to a memory through a parallel interface, and the CPU-side protocol processor and the memory-side protocol processor are connected through a serial link.
Public/Granted literature
- US20170255574A1 MEMORY INTERFACE APPARATUS Public/Granted day:2017-09-07
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