- Patent Title: Generic width independent parallel checker for a device under test
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Application No.: US15375542Application Date: 2016-12-12
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Publication No.: US10222415B2Publication Date: 2019-03-05
- Inventor: Tejinder Kumar , Suchi Prabhu Tandel , Rakesh Malik
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Agency: Crowe & Dunlevy
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3193

Abstract:
Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.
Public/Granted literature
- US20180164370A1 GENERIC WIDTH INDEPENDENT PARALLEL CHECKER FOR A DEVICE UNDER TEST Public/Granted day:2018-06-14
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