公开(公告)号：US10222415B2

公开(公告)日：2019-03-05

申请号：US15375542

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Suchi Prabhu Tandel ,  Rakesh Malik

IPC: G01R31/317 ,  G01R31/3193

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

公开(公告)号：US20180164370A1

公开(公告)日：2018-06-14

申请号：US15375542

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Suchi Prabhu Tandel ,  Rakesh Malik

IPC: G01R31/317 ,  G01R31/3193

CPC classification number: G01R31/31703 ,  G01R31/3171 ,  G01R31/31932 ,  G01R31/31935 ,  G11C15/00 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/0405 ,  G11C2029/2602

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.