Invention Grant
- Patent Title: Sintered solder for fine pitch first-level interconnect (FLI) applications
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Application No.: US15394460Application Date: 2016-12-29
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Publication No.: US10224299B2Publication Date: 2019-03-05
- Inventor: Mihir A. Oka , Ken P. Hackenberg , Vijay Krishnan (Vijay) Subramanian , Neha M. Patel , Nachiket R. Raravikar
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/00

Abstract:
Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
Public/Granted literature
- US20180190604A1 SINTERED SOLDER FOR FINE PITCH FIRST-LEVEL INTERCONNECT (FLI) APPLICATIONS Public/Granted day:2018-07-05
Information query
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