公开(公告)号：US20190157232A1

公开(公告)日：2019-05-23

申请号：US16320680

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Dae-Wood Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/3512

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US11784150B2

公开(公告)日：2023-10-10

申请号：US17825739

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/3512

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US10797014B2

公开(公告)日：2020-10-06

申请号：US16320680

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US10515914B2

公开(公告)日：2019-12-24

申请号：US16260908

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Mihir A. Oka ,  Ken P. Hackenberg ,  Vijay Krishnan (Vijay) Subramanian ,  Neha M. Patel ,  Nachiket R. Raravikar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

公开(公告)号：US10224299B2

公开(公告)日：2019-03-05

申请号：US15394460

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Mihir A. Oka ,  Ken P. Hackenberg ,  Vijay Krishnan (Vijay) Subramanian ,  Neha M. Patel ,  Nachiket R. Raravikar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

公开(公告)号：US11380643B2

公开(公告)日：2022-07-05

申请号：US17009321

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.