Invention Grant
- Patent Title: Method for manufacturing semiconductor device having gate structure with reduced threshold voltage
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Application No.: US15681570Application Date: 2017-08-21
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Publication No.: US10224324B2Publication Date: 2019-03-05
- Inventor: Wei-Hsin Liu , Pi-Hsuan Lai
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsinchu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/11 ; H01L21/033 ; H01L27/088 ; H01L21/8234

Abstract:
A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
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Information query
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