Invention Grant
- Patent Title: Supporting binary translation alias detection in an out-of-order processor
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Application No.: US15282266Application Date: 2016-09-30
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Publication No.: US10228956B2Publication Date: 2019-03-12
- Inventor: Vineeth Mekkat , Mark J. Dechene , Zhongying Zhang , Jason Agron , Sebastian Winkel
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F9/312
- IPC: G06F9/312 ; G06F9/44 ; G06F9/455 ; G06F9/38 ; G06F8/41 ; G06F8/52 ; G06F9/30

Abstract:
In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.
Public/Granted literature
- US20180095765A1 SUPPORTING BINARY TRANSLATION ALIAS DETECTION IN AN OUT-OF-ORDER PROCESSOR Public/Granted day:2018-04-05
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