公开(公告)号：US11693780B2

公开(公告)日：2023-07-04

申请号：US17391962

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US10915320B2

公开(公告)日：2021-02-09

申请号：US16231305

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Xi Chen ,  Manjunath Shevgoor

IPC: G06F9/302 ,  G06F9/315 ,  G06F9/30 ,  G06F9/54 ,  G06F9/38

Abstract: A processor includes an instruction fetch circuit to retrieve instructions from memory, and a decode unit circuit to decode retrieved instructions. The decode unit circuit identifies a shift instruction, accumulates a shift folded immediate value to track a number of bit positions shifted for a source register, and prevents the shift instruction from allocation to an execution unit of the processor.

公开(公告)号：US20160364240A1

公开(公告)日：2016-12-15

申请号：US14737058

申请日：2015-06-11

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Girish Venkatasubramanian ,  Howard H. Chen

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F8/41 ,  G06F8/443 ,  G06F9/30058 ,  G06F9/3846

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.

Abstract translation: 本文公开了方法，装置，系统和制品。 示例性设备包括指令分析器，用于识别要由硬件处理器执行的指令内的预测块。 示例性装置包括：性能监视器，用于基于与所述预测块相关联的指令地址来访问误差预测统计量。 示例性装置包括区域形成器，响应于确定误差预测统计量高于误差预测阈值，将所述预测块包括在用于优化的预测区域中。

公开(公告)号：US20200210339A1

公开(公告)日：2020-07-02

申请号：US16234135

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US10235177B2

公开(公告)日：2019-03-19

申请号：US15201403

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Janghaeng Lee ,  Youfeng Wu

IPC: G06F9/30 ,  G06F9/38 ,  G06F8/41

Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.

公开(公告)号：US09996356B2

公开(公告)日：2018-06-12

申请号：US14998299

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Jason M. Agron ,  Ethan Schuchman ,  Sebastian Winkel ,  Youfeng Wu ,  Gisle Dankel

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

公开(公告)号：US20180004524A1

公开(公告)日：2018-01-04

申请号：US15201403

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Janghaeng Lee ,  Youfeng Wu

IPC: G06F9/30

CPC classification number: G06F9/30123 ,  G06F8/41 ,  G06F9/3016 ,  G06F9/384

Abstract: In an example, there is disclosed an apparatus, including a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. There is also disclosed a processor to reclaim the physical register based at least in part on the reclamation hint.

公开(公告)号：US20170351516A1

公开(公告)日：2017-12-07

申请号：US15175899

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Ching-Tsun Chou ,  Youfeng Wu

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0831 ,  G06F12/0875

CPC classification number: G06F9/30043 ,  G06F9/3017 ,  G06F9/327 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855

Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

公开(公告)号：US20230409481A1

公开(公告)日：2023-12-21

申请号：US18320780

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Stanislav Shwartsman ,  Anant Nori ,  Shankar Balachandran ,  Elad Shtiegmann ,  Vineeth Mekkat ,  Manjunath Shevgoor ,  Sourabh Alurkar

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

公开(公告)号：US10540178B2

公开(公告)日：2020-01-21

申请号：US15265587

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Youfeng Wu ,  Sebastian Winkel ,  Oleg Margulis

IPC: G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.