Invention Grant
- Patent Title: Method of evaluating thin-film transistor, method of manufacturing thin-film transistor, and thin-film transistor
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Application No.: US14915704Application Date: 2014-06-25
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Publication No.: US10230003B2Publication Date: 2019-03-12
- Inventor: Eiji Takeda , Toru Saito
- Applicant: JOLED INC.
- Applicant Address: JP Tokyo
- Assignee: JOLED INC.
- Current Assignee: JOLED INC.
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2013-182256 20130903
- International Application: PCT/JP2014/003395 WO 20140625
- International Announcement: WO2015/033499 WO 20150312
- Main IPC: G01R27/04
- IPC: G01R27/04 ; H01L29/786 ; H01L21/66 ; G01R31/26 ; G01R31/265 ; H01L21/477 ; H01L29/24 ; H01L29/66 ; H01L21/02

Abstract:
A method of evaluating a thin-film transistor (TFT) which is disposed on a substrate, and includes at least: an oxide semiconductor layer which functions as a channel layer; and a channel protection layer disposed above the oxide semiconductor layer. The method includes: measuring a change in a reflectance of a microwave emitted to the oxide semiconductor layer while the oxide semiconductor layer is irradiated with excitation light by pulse irradiation; calculating a decay period which is a period of time taken for the reflectance to decay to 1/e or 1/e2, based on the change in the reflectance obtained in the measuring; and performing determination related to a threshold voltage of the oxide semiconductor layer, based on the decay period calculated in the calculating.
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