- Patent Title: Apparatuses and methods for chip identification in a memory package
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Application No.: US15973061Application Date: 2018-05-07
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Publication No.: US10236039B2Publication Date: 2019-03-19
- Inventor: Masaru Morohashi
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/20 ; G11C7/24 ; G11C8/12

Abstract:
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes a identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.
Public/Granted literature
- US20180254074A1 APPARATUSES AND METHODS FOR CHIP IDENTIFICATION IN A MEMORY PACKAGE Public/Granted day:2018-09-06
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