公开(公告)号：US20190237132A1

公开(公告)日：2019-08-01

申请号：US15884192

申请日：2018-01-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4076 ,  G06F3/06 ,  G11C7/02

CPC classification number: G11C11/40615 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4091

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a normal memory region assigned to first value of a redundant signal and a redundancy memory region assigned to a second value of the redundant signal; a first circuit configured to receive a row address signal, produce the first value of the redundant signal if the first circuit detects that the row address signal is inconsistent to any of redundancy information, and produce the second value of the redundant signal and additional row address signal if the first circuit detects that the row address signal is consistent to any of the redundancy information; and a second circuit configured to produce further additional row address signal based on the row address signal and the first value of the redundant signal or based on the additional row address signal and the second value of the redundant signal.

公开(公告)号：US10236039B2

公开(公告)日：2019-03-19

申请号：US15973061

申请日：2018-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi

IPC: G11C7/10 ,  G11C7/20 ,  G11C7/24 ,  G11C8/12

Abstract: Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes a identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.

公开(公告)号：US20200302994A1

公开(公告)日：2020-09-24

申请号：US16358587

申请日：2019-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406 ,  G11C11/408 ,  G06F7/58

Abstract: Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US10580475B2

公开(公告)日：2020-03-03

申请号：US15876566

申请日：2018-01-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi ,  Hidekazu Noguchi

IPC: G06F13/00 ,  G11C11/406 ,  G11C15/04 ,  G11C8/10 ,  G06F13/16 ,  G11C16/34

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

公开(公告)号：US10360954B2

公开(公告)日：2019-07-23

申请号：US16192639

申请日：2018-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi

IPC: G11C7/10 ,  G11C7/20 ,  G11C7/24 ,  G11C8/12

Abstract: Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes an identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.

公开(公告)号：US11521669B2

公开(公告)日：2022-12-06

申请号：US17301533

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406 ,  G06F7/58 ,  G11C11/408

Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US11322192B2

公开(公告)日：2022-05-03

申请号：US16805197

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： Masaru Morohashi ,  Hidekazu Noguchi

IPC: G06F13/00 ,  G11C11/406 ,  G11C15/04 ,  G11C8/10 ,  G06F13/16 ,  G11C16/34

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

公开(公告)号：US20210350844A1

公开(公告)日：2021-11-11

申请号：US17443056

申请日：2021-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi ,  Ryo Nagoshi ,  Yuan He ,  Yutaka Ito

IPC: G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

公开(公告)号：US11152050B2

公开(公告)日：2021-10-19

申请号：US16012679

申请日：2018-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi ,  Ryo Nagoshi ,  Yuan He ,  Yutaka Ito

IPC: G11C7/00 ,  G11C11/406

Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

公开(公告)号：US10381064B1

公开(公告)日：2019-08-13

申请号：US15875985

申请日：2018-01-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4076

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.