- Patent Title: Passive components in vias in a stacked integrated circuit package
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Application No.: US14583015Application Date: 2014-12-24
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Publication No.: US10236209B2Publication Date: 2019-03-19
- Inventor: Sujit Sharan , Ravindranath Mahajan , Stefan Rusu , Donald S. Gardner
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/48 ; H01L25/16 ; H01L49/02 ; H01L23/538 ; H01L23/522 ; H01L27/08

Abstract:
Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
Public/Granted literature
- US20160190113A1 PASSIVE COMPONENTS IN VIAS IN A STACKED INTEGRATED CIRCUIT PACKAGE Public/Granted day:2016-06-30
Information query
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