Invention Grant
- Patent Title: Apparatus and methods to support counted loop exits in a multi-strand loop processor
-
Application No.: US15391703Application Date: 2016-12-27
-
Publication No.: US10241794B2Publication Date: 2019-03-26
- Inventor: Sergey P. Scherbinin , Jayesh Iyer , Alexander Y. Ostanevich , Dmitry Maslennikov , Denis G. Motin , Alexander V. Ermolovich , Andrey Chudnovets , Sergey A. Rozhkov , Boris A. Babayan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/54 ; G06F9/32 ; G06F8/41 ; G06F9/38 ; G06F9/30 ; G06F9/455

Abstract:
Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.
Public/Granted literature
- US20180181400A1 APPARATUS AND METHODS TO SUPPORT COUNTED LOOP EXITS IN A MULTI-STRAND LOOP PROCESSOR Public/Granted day:2018-06-28
Information query